Microchips' size reduction has been traditionally the most important challenge in the semiconductor industry; however, reliability issues and robustness of the circuits present a bottleneck in the integrated circuit (IC) miniaturization tendency. The IC's vulnerability to electrostatic discharge (ESD) is one of the most critical reliability problems. ESD is an event that transfers a finite amount of charge from one object (i.e., human body, transmission lines, or metallic pieces) to the other (i.e., microchip). The process results in a huge current, and when a microchip is subjected to ESD, the microchip is likely to be damaged. Several ESD standards have been defined in the semiconductor industry to model this random phenomenon; they include the human body model (HBM, charge transfers from human body to ground via microchip), machine model (MM, charge transfers from an equipment or metallic tool to ground via microchip), charged device model (CDM, charge is built up on microchip and transfers to ground), and international electrochemical commission (IEC, charge transfers from a charged capacitor through an air discharge to ground via microchip).
Large-scale integration of CMOS devices and the increasing number of external pins have resulted in integrated circuits (ICs) which are very sensitive to ESD events. At times, numerous ICs have been migrated to state-of-the-art CMOS technologies, but direct scaling can reduce the level of ESD protection accordingly. As a result, IC's production tape outs are being considerably delayed mainly because products do not meet the ESD protection requirements.
An IC's ESD protection typically includes supply clamps and Input/Outputs (I/O) pad protection. These ESD protection components should have low leakage current at normal operating voltages and provide very high conductance paths during an ESD event. This guarantees the integrity of the core circuit functionality during handling, assembling, and circuit operation. For sub-micron fully silicided CMOS ICs, ESD protection is even more critical. In these ICs, fabrication process improvements required for device scaling have in turn increased the ESD sensitivity, and reduced the level of stress that typical ESD protection devices can safely support. See, for example:                1. S. Voldman, “A Review of Electrostatic Discharge (ESD) in Advanced Semiconductor Technology,” Microelectronics Reliability, vol. 44, pp. 33–46, 2004;        2. S. Voldman, W. Anderson, R. Ashton, M. Chaine, C. Duvvury, T. Maloney, E. Worley, “A Strategy for Characterization and Evaluation of ESD Robustness of CMOS Semiconductor Technologies,” EOS/ESD Symposium, pp. 212–224, 1999; and        3. K. Bock, B. Keppens, V. De Heyn, G. Groeseneken, L. Y. Ching, A. Naem, “Influence of Gate Length on ESD-Performance for Deep Sub-Micron CMOS Technology,” EOS/ESD Symposium, pp. 95–104, 1999.        
Due to the ESD sensitivity of ICs in sub-micron CMOS technologies, devices for on-chip ESD protection occupy a considerable area of the IC. Furthermore, even increasing the size of the traditional protection structures to levels comparable with the core circuit dimensions does not guarantee that the ESD requirements are met. This condition creates a bottleneck for the IC's development and diminishes the potential advantages of the CMOS scaling.
Limitations of typical ESD protection structures can be overcome by designing devices in which the I–V characteristics show voltage snapback. See, for example:                4. V. Vashchenko, A. Concannon, M. Ter Beek and P. Hopper, “LVTSCR structure for latch-up free ESD protection of BiCMOS RF circuits,” Microelectronics Reliability, vol. 43, pp. 61–69, 2003; and        5. M. -D. Ker and H. -H. Chang, “Cascode LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger,” Solid-State Electronics, vol. 44, pp. 425–445, 2000.These devices present a way to build smaller area I/O protection and supply clamps.        
Several on-chip structures have been used to protect integrated circuits from random and fast-transient high voltages caused by ESD, but few are capable of protecting integrated circuits effectively and efficiently against the most demanding ESD models without latch-up. Existing low-voltage trigger thyristor- or Silicon Controlled Rectifier (SCR) devices typically have a very low holding voltage, which would allow latch-up conditions during an ESD event while power was applied. Alternative solutions previously suggested to overcome this drawback include the use of additional components and empirical modification of the lateral structure of the SCR. The former approach adds complexity and consumes additional area on the die and may cause increases in leakage current and parasitic capacitance, and the latter approach is very time-consuming and only possible for some limited cases.
The thyristor- or SCR-type structures snap back to a low holding voltage and high conductance conditions during the on-state. For these devices, once the trigger voltage is reached, high injection of carriers takes place at the anode and cathode regions at low electric field. The low electric field condition held by the device during the on-state allows higher peak current conduction at lower power regimes. Furthermore, the current density in these devices is more uniformly distributed across the cross-sectional area, which permits better dispersion of the heat dissipation, and to some extent avoids hot-spot generation during ESD events.
The Low-Voltage-Trigger-Silicon-Controlled-Rectifier (LVTSCR) uses the advantages of the SCR-type devices but also reduces the trigger voltage to levels acceptable for use in CMOS IC protection. See, for example:                6. A. Chatterjee and T. Polgreen, “A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads,” IEEE Electron Device Letters, vol. 12, pp. 21–22 Jan. 1991.This device provides one of the best alternatives for the design of I/O protection and supply clamps. The LVTSCR I–V characteristics show a low holding voltage and a low holding current (Ref 4–6). These characteristics are convenient for some submicron CMOS technologies, but for circuits with operating voltages above about 1.5V, ESD protection implemented with this device has the risk of latch-up problems.        